Many applications employ an analog-to-digital converter (ADC) to convert an analog input signal representing a real-world quantity, such as audio, an image, a moving picture, etc., to a digital signal that can be processed digitally. One type of analog-to-digital converter commonly used is known as a charge-redistribution successive approximation register analog-to-digital converter (SAR ADC).
A typical SAR ADC includes a digital-to-analog converter (DAC), a comparator, and a logic circuit. The DAC includes a reference voltage source. The DAC generates an analog signal that depends on the reference voltage provided by the reference voltage source, and an M-bit digital value received from the logic circuit. The DAC has M converter stages plus an additional converter stage. Each of the M converter stages is involved in generating a respective bit of the digital value. The comparator compares a sample of an analog input signal input to the ADC with the analog signal generated by the DAC to generate a comparator output. The ADC repetitively performs conversion cycles in which the ADC digitizes a single sample of the analog input signal to generate a respective digital value. Each conversion cycle includes, in order, a sampling process, a conversion process, and a reset process. In the sampling process, the ADC samples the analog input signal to generate a respective sample. In the conversion process, the ADC generates a respective M-bit digital value that represents the sample of the analog input signal obtained in the sampling process. The DAC begins each conversion cycle in a reset state. During the conversion process, the comparator is strobed M times to produce M comparator outputs. Each time the comparator is strobed, the logic circuit operates in response to the comparator output to set a respective bit of the digital value input to the DAC so that the analog signal output by the DAC in response to the digital value better approximates the sample of the analog input signal. In the reset process at the end of each conversion cycle, the converter stages of the DAC receive a common reset pulse that restores the converter stages to the reset state simultaneously.
The charge drawn from the reference voltage source during each converter cycle is dependent on the sample of the analog input signal. A parameter that depends on the sample of the analog input signal will be described herein as being sample dependent, or having sample dependence. Since the output impedance of the reference voltage source is greater than zero, the reference voltage is also sample dependent. The reference voltage being sample dependent causes undesired harmonic distortion. The problem is particularly serious in high-speed, high-performance ADCs, such as the ADCs used in measurement instrumentation, in which the charge drawn from the reference voltage source is large. Reducing the output impedance of the reference voltage source can ameliorate this problem, but only at the expense of an undesirable increase in power consumption.
Other techniques for reducing the sample dependence of the charge drawn from the reference voltage source are known, but such techniques typically only reduce the sample dependence of the charge drawn from the reference voltage supply during the conversion process. Such conventional techniques typically do not reduce an additional sample dependence, namely, the sample dependence of the charge drawn from the reference voltage source during the reset process. FIG. 1 is a graph showing the variation of the total charge Qtotal drawn from the reference voltage source of a conventional charge redistribution SAR ADC during each conversion cycle on the sample Vin of the analog input signal. The sample-dependent charge drawn through the non-zero output resistance of the reference voltage source undesirably causes the reference voltage used to convert the sample of the analog input signal in the next conversion cycle to depend on the sample of the analog input signal converted in the current conversion cycle.
Accordingly, what is needed is a charge redistribution SAR ADC in which the total charge drawn from the reference voltage source throughout each conversion cycle, including during the reset process, has a reduced dependence on the sample of the analog input signal converted in the conversion cycle.